Verification IP (VIP) : VIP development, customization and verification.
IP Design Verification: Build testbench from scratch, enhance legacy testbench, Port testbench across methodology and verify same with self-checking mechanism.
Subsystem Verification: Integrate IPs and Glue logic, Develop Testbench re-using IP level Testbench infrastructure as much as possible, Ensure Connectivity, Functionality, Performance.
SOC level verification: Develop C-SV based Testbench in UVM/OVM, Ensure Connectivity, Functionality, Performance, Develop use case scenarios
Domain Specific Service Key Notes
- Verify the functionality w.r.t different FPGA.
- Ensure all the artefacts are compliance with DO-254 avionics standard.
- Development of the verification environment as per the avionics standard coding guideline.
- All implementations are in line with agile review process to make sure there is no process violation.
- Take the complete ownership of the verification issues that have been raised, do follow up with the designers to have a close on the issues.