- Test plan/DFT Architecture and DFX methodology development.
- JTAG planning and implementation for AC and DC.
- Scan insertion: Scan chain generation.
- Test pin optimization for less IOs.
- ATPG, Test pattern verification, simulation.
- MBIST insertion: Controller logic and optimization.
- Silicon Bring up, wafer sort, package test and Production Program optimization support for tester
- Formal Verification/equivalence check at each stage of design.
- DFT mode STA constraint generation and verification.
- AMS IP testing and Verification from parametric testing point of view.